Deep Vision
Fabless edge-AI chip developer whose discrete neural processing units accelerated on-device vision and generative inference.
Founded
2015Fabless edge-AI chip developer whose discrete neural processing units accelerated on-device vision and generative inference.
The architecture is programmable rather than fixed-function, mapping inference graphs onto proprietary multiply-accumulate units through a dataflow design. That lets a single silicon generation track shifting model families without a redesign as workloads moved from convolutional networks to transformer and multimodal models.
A companion software development kit supplies compilers, quantisation tooling, and a pre-optimised model library, which lowers the effort of moving trained models onto the hardware. Positioning the accelerators as companions to existing host processors also lets integrators add AI capability without replacing their application processor.
Source: nxp.com
Discrete neural processing units compete with inference engines integrated into application processors and with general-purpose GPUs, so the addressable market depends on buyers wanting acceleration separable from their host silicon. That narrows the funnel to systems where on-device AI is a primary requirement rather than an optional feature.
The product line must also keep pace with a model landscape that changes quickly, and silicon designed years before tape-out can age against newer architectures. Following acquisition by a larger semiconductor vendor, the roadmap now advances within the parent portfolio's priorities rather than independently.
Source: nxp.com
The company designs discrete neural processing units that accelerate deep-learning inference on devices rather than in the cloud, pairing its silicon with a software development kit for model optimization and deployment. Its processors address vision-centric workloads first and generative AI later as the architecture generations advanced.
Target applications include AI-enabled cameras, embedded vision, industrial automation, and automotive systems, where local inference reduces latency and bandwidth demand and keeps data on device. The chips are designed to sit alongside a host application processor and take on inference while that processor handles general-purpose compute.
Source: nxp.com