
PowerLattice develops power delivery chiplets that integrate voltage regulation inside AI processor packages.
PowerLattice makes a power delivery chiplet that moves voltage regulation from the circuit board and package substrate into the processor package. The chiplet combines miniature on-die magnetic inductors, analog control circuitry, a vertical die stack, and a programmable configuration layer, so current reaches compute silicon over a very short path instead of a long board-level power plane.
The company says the approach reduces total power demand for AI compute by more than half. It reports early silicon in production with foundry partners and engineering samples shipped to prospective customers.
On-package power delivery targets the conversion losses that grow as AI accelerator current rises and board-level voltage regulation becomes inefficient, a problem made urgent by the cooling and grid-capacity bottlenecks now constraining AI data centers.
The chiplet is aimed at designers of AI accelerators, GPUs, and data-center processors. Because it adds a power stage to existing chip architectures rather than replacing the compute die, customers can adopt it without redesigning their processor, and several chiplets can run in parallel to form the separate power domains of one device.
Integrating regulation inside the package shortens the power delivery path, which lowers resistive loss and improves transient response for rapidly changing AI workloads. PowerLattice credits its founders' prior work on integrated magnetics and analog control at Qualcomm, NUVIA, and Intel, and cites issued and pending patents covering the approach.
Investors framed the round around that same constraint: Playground Global general partner Pat Gelsinger and Celesta Capital partner Dr. Steve Fu both described power as the defining limit on AI scaling, with Celesta reporting $31 million in total funding for the company to date.