Celero Communications Inc., a startup that develops data center networking chips, today announced that it has raised $275 million in funding.
The Series C round was led by Alphabet Inc.’s CapitalG fund, Atreides Management and Valor Equity Partners. Returning backers Sutter Hill Ventures and Maverick Silicon chipped in as well. Celero is now valued at $3 billion.
Data center operators link together their facilities using fiber-optic cables that can span more than 100 miles. Those fiber-optic cables are managed by specialized chips called coherent digital signal processors, or DSPs.
Irvine, California-based Celero is developing a coherent DSP specifically optimized for artificial intelligence workloads. The company says its technology provides lower latency than current chips and uses less power.
Coherent DSPs are responsible for managing a data center’s transceivers. Those are optical modules designed to turn digital data, which is stored as electricity, into light that can travel over fiber-optic cables. Once the light arrives at its destination, transceivers turn it back into electricity.
Many workloads require the ability to determine when inbound network requests were generated. The simplest way to obtain that information is to create a physical network link through which servers can exchange timing data. However, that approach comes with tradeoffs: it adds complexity to network designs and raises costs. Coherent DSPs make it possible to obtain timing information without extra hardware.
Such chips also play an important role in maintaining network reliability. Light disperses and dims inside fiber-optic cables, which causes some of the data that it contains to be lost. Coherent DSPs address that issue. They do so by extending data streams with extra bits that enable the recipient to fix certain transmission errors.
Celero says its coherent DSP can power not only long-haul links between data centers but also their internal networks. In particular, the chip supports scale-up and scale-out networking. Scale-up describes the hardware that connects chips in the same rack. Scale-out networks link together different racks.
Under the hood, Celero’s coherent DSP combines standard digital transistors with analog circuitry. Digital transistors process discrete electrical signals that each represent a one or a zero. By contrast, analog circuitry processes a continuous current that fluctuates over time. Celero’s chip uses the analog circuitry to connect to the optical hardware that it manages.
The company’s product engineering efforts reached a major milestone ahead of today’s funding announcement. It validated a version of its chip that can be made using a two-nanometer process, the most advanced semiconductor production technology on the market. Taiwan Semiconductor Manufacturing Co.’s two-nanometer node provides 15% better performance than its predecessor.
Celera says its two-nanometer design can support 1.6T and 3.2T interconnects. Such technologies transmit up to 3.2 terabits of data per second per port. Today’s AI networks are significantly slower.
“AI infrastructure is rapidly outgrowing the capabilities of traditional optical interconnect architectures,” said Celero co-founder and Chief Executive Officer Nariman Yousefi. “Our two-nanometer silicon validation demonstrates that coherent technology can deliver the bandwidth density, power efficiency and scalability required for the next generation of AI networks.”
Celero will use the funding round to speed up its product development and manufacturing roadmap.
