PowerLattice

Integrating regulation inside the package shortens the power delivery path, which lowers resistive loss and improves transient response for rapidly changing AI workloads. PowerLattice credits its founders' prior work on integrated magnetics and analog control at Qualcomm, NUVIA, and Intel, and cites issued and pending patents covering the approach.

Investors framed the round around that same constraint: Playground Global general partner Pat Gelsinger and Celesta Capital partner Dr. Steve Fu both described power as the defining limit on AI scaling, with Celesta reporting $31 million in total funding for the company to date.

On-package power delivery targets the conversion losses that grow as AI accelerator current rises and board-level voltage regulation becomes inefficient, a problem made urgent by the cooling and grid-capacity bottlenecks now constraining AI data centers.

The chiplet is aimed at designers of AI accelerators, GPUs, and data-center processors. Because it adds a power stage to existing chip architectures rather than replacing the compute die, customers can adopt it without redesigning their processor, and several chiplets can run in parallel to form the separate power domains of one device.

PowerLattice's power delivery chiplet moves voltage regulation into an AI processor package, close to the compute die. It combines proprietary miniaturized magnetic inductors, voltage-control circuits, a vertical chiplet design, and programmable configuration. The company presents this as a way to shorten resistive power paths and reduce power losses.

The chiplet is intended for AI accelerators, GPUs, CPUs, and other high-power processors. PowerLattice said in November 2025 that it had silicon in hand and was preparing engineering samples for devices drawing more than one kilowatt.